| logisim-evolution/logisim-evolution |
6,725 |
|
0 |
0 |
3 months ago |
0 |
|
209 |
gpl-3.0 |
Java |
| Digital logic design tool and simulator |
| open-sdr/openwifi |
3,363 |
|
0 |
0 |
over 2 years ago |
0 |
|
51 |
agpl-3.0 |
C |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software |
| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| SpinalHDL/SpinalHDL |
1,912 |
|
0 |
4 |
3 months ago |
140 |
November 01, 2023 |
106 |
other |
Scala |
| Scala based HDL |
| jbush001/NyuziProcessor |
1,863 |
|
0 |
0 |
about 2 years ago |
0 |
|
90 |
apache-2.0 |
C |
| GPGPU microprocessor architecture |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| SI-RISCV/e200_opensource |
1,688 |
|
0 |
0 |
about 5 years ago |
0 |
|
33 |
apache-2.0 |
Verilog |
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| FPGAwars/icestudio |
1,621 |
|
0 |
0 |
about 2 years ago |
0 |
|
117 |
gpl-2.0 |
JavaScript |
| :snowflake: Visual editor for open FPGA boards |
| geohot/fromthetransistor |
1,607 |
|
0 |
0 |
over 4 years ago |
0 |
|
16 |
|
|
| From the Transistor to the Web Browser, a rough outline for a 12 week course |
| corundum/corundum |
1,354 |
|
0 |
0 |
over 2 years ago |
0 |
|
84 |
other |
Verilog |
| Open source FPGA-based NIC and platform for in-network compute |
