| vortexgpgpu/vortex |
939 |
|
0 |
0 |
about 2 years ago |
0 |
|
51 |
apache-2.0 |
Verilog |
| charcole/Z3 |
111 |
|
0 |
0 |
over 11 years ago |
0 |
|
0 |
bsd-3-clause |
C |
| A Verilog implementation of the Infocom Z-Machine V3. With BIOS and benchmarks. Verified in hardware. |
| lsils/benchmarks |
102 |
|
0 |
0 |
almost 3 years ago |
0 |
|
2 |
mit |
Verilog |
| EPFL logic synthesis benchmarks |
| meelgroup/manthan |
26 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
other |
Python |
| Manthan for Boolean function synthesis |
| ispras/hdl-benchmarks |
18 |
|
0 |
0 |
over 2 years ago |
0 |
|
4 |
other |
Verilog |
| Collection of open HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing. |
| PrincetonUniversity/OPDB |
18 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
|
Verilog |
| OpenPiton Design Benchmark |
| jinwookjungs/datc_robust_design_flow |
15 |
|
0 |
0 |
about 6 years ago |
0 |
|
2 |
gpl-3.0 |
Verilog |
| DATC Robust Design Flow. |
| ieee-ceda-datc/RDF-2019 |
14 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
mit |
Verilog |
| DATC RDF |
| YosysHQ/yosys-bench |
12 |
|
0 |
0 |
about 6 years ago |
0 |
|
4 |
isc |
Verilog |
| Benchmarks for Yosys development |
| zhemao/md5cracker |
10 |
|
0 |
0 |
about 11 years ago |
0 |
|
0 |
|
Verilog |
| A Hardware MD5 Cracker for the Cyclone V SoC |
