| riscv/riscv-bitmanip |
174 |
|
0 |
0 |
over 3 years ago |
0 |
|
44 |
cc-by-4.0 |
Makefile |
| Working draft of the proposed RISC-V Bitmanipulation extension |
| OpenFPGAduino/OpenFPGAduino |
135 |
|
0 |
0 |
over 7 years ago |
0 |
|
6 |
agpl-3.0 |
Makefile |
| All open source file and project for OpenFPGAduino project |
| bespoke-silicon-group/bsg_sv2v |
23 |
|
0 |
0 |
about 3 years ago |
0 |
|
2 |
bsd-3-clause |
Python |
| A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible. |
| halfmanhalftaco/fpga-docker |
20 |
|
0 |
0 |
over 4 years ago |
0 |
|
1 |
|
Makefile |
| Tools for running FPGA vendor toolchains with Docker |
| n24bass/ice40_8bitworkshop |
8 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
other |
Verilog |
| "Designing Video Game Hardware in Verilog" in iCE40HX8K Breakout Board. |
| XarkLabs/upduino-example |
6 |
|
0 |
0 |
almost 3 years ago |
0 |
|
0 |
other |
Makefile |
| Example UPduino project setup for Linux, macOS and WIndows+WSL for synthesis and simulation |
| balanx/vbpp |
6 |
|
0 |
0 |
over 10 years ago |
0 |
|
0 |
other |
C |
| Verilog PreProcessor. |
| maruuusa83/pyjer |
5 |
|
0 |
0 |
almost 10 years ago |
0 |
|
4 |
mit |
Makefile |
| A Framework for Prototyping of IoT Devices with High Level Synthesis Tools and SoC |
