| ahegazy/aes |
20 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
Verilog |
| Advanced encryption standard implementation in verilog. |
| biren15/Design-and-Verification-of-LDPC-Decoder |
17 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
|
Verilog |
| - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab. |
| leo47007/TPU-Tensor-Processing-Unit |
14 |
|
0 |
0 |
over 6 years ago |
0 |
|
0 |
|
Verilog |
| IC implementation of TPU |
| lzw545/opengg |
11 |
|
0 |
0 |
over 15 years ago |
0 |
|
0 |
|
Verilog |
| OpenGL-like graphics pipeline on a Xilinx FPGA |
| pontazaricardo/Verilog_Calculator_Matrix_Multiplication |
8 |
|
0 |
0 |
over 8 years ago |
0 |
|
1 |
mpl-2.0 |
Verilog |
| This is a simple project that shows how to multiply two 3x3 matrixes in Verilog. |
| ac-optimus/Convolution-using-systolic-arrays |
8 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| attie/led_matrix_tinyfpga_a2 |
7 |
|
0 |
0 |
about 7 years ago |
0 |
|
1 |
|
Verilog |
| Driving an LED Matrix with a TinyFPGA |
| aanunez/KeypadScanner |
6 |
|
0 |
0 |
almost 5 years ago |
0 |
|
0 |
gpl-2.0 |
Verilog |
| Verilog code for scanning a four by four matrix keypad. |
