| secworks/aes |
238 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
bsd-2-clause |
Verilog |
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys. |
| ahegazy/aes |
20 |
|
0 |
0 |
over 3 years ago |
0 |
|
1 |
mit |
Verilog |
| Advanced encryption standard implementation in verilog. |
| ascend-secure-processor/oram |
12 |
|
0 |
0 |
almost 9 years ago |
0 |
|
3 |
|
Verilog |
| Hardware implementation of ORAM |
| hplp/aes_chisel |
10 |
|
0 |
0 |
almost 4 years ago |
2 |
April 04, 2019 |
0 |
apache-2.0 |
Scala |
| Implementation of the Advanced Encryption Standard in Chisel |
| kwonalbert/oram |
9 |
|
0 |
0 |
over 10 years ago |
0 |
|
1 |
|
Verilog |
| Recursive unified ORAM |
| Groundworkstech/rc4-prbs |
7 |
|
0 |
0 |
over 12 years ago |
0 |
|
0 |
lgpl-3.0 |
Verilog |
| A Verilog open-source implementation of a RC4 encryption algorigthm using a pseudorandom binary sequence (PRBS) for FPGA synthesis. |
| raymondrc/FPGA_SM4 |
6 |
|
0 |
0 |
about 8 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| FPGA implementation of Chinese SM4 encryption algorithm. |
| gongxunwu/sm4-verilog |
5 |
|
0 |
0 |
about 7 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
