| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| secworks/trng | 26 | 0 | 0 | over 5 years ago | 0 | 0 | bsd-2-clause | Verilog | ||
| True Random Number Generator core implemented in Verilog. | ||||||||||
| ucb-cs250/caravel_fpga250 | 7 | 0 | 0 | over 5 years ago | 0 | 0 | apache-2.0 | Verilog | ||
| FPGA250 aboard the eFabless Caravel | ||||||||||
| dpiegdon/verilog-buildingblocks | 6 | 0 | 0 | almost 6 years ago | 0 | 0 | lgpl-3.0 | Verilog | ||
| Library of generic verilog buildingblocks | ||||||||||
| siamumar/BIST_PUF_TRNG | 5 | 0 | 0 | over 8 years ago | 0 | 0 | Verilog | |||
| A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators | ||||||||||
| teknohog/rautanoppa | 5 | 0 | 0 | almost 11 years ago | 0 | 0 | gpl-3.0 | Verilog | ||
| Hardware random number generator for FPGAs | ||||||||||
