| cocotb/cocotb |
1,519 |
|
9 |
22 |
about 2 years ago |
44 |
October 06, 2023 |
415 |
bsd-3-clause |
Python |
| cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
| VUnit/vunit |
651 |
|
1 |
5 |
over 2 years ago |
87 |
April 23, 2023 |
216 |
other |
VHDL |
| VUnit is a unit testing framework for VHDL/SystemVerilog |
| chiselverify/chiselverify |
114 |
|
0 |
0 |
over 2 years ago |
3 |
October 10, 2022 |
4 |
bsd-2-clause |
Scala |
| A dynamic verification library for Chisel. |
| steveicarus/ivtest |
95 |
|
0 |
0 |
about 4 years ago |
0 |
|
0 |
gpl-2.0 |
Verilog |
| Regression test suite for Icarus Verilog. (OBSOLETE) |
| ku-fpg/kansas-lava |
42 |
|
0 |
0 |
over 6 years ago |
5 |
April 06, 2018 |
16 |
other |
Haskell |
| Kansas Lava |
| CMU-SAFARI/DRAM-Bender |
21 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
mit |
VHDL |
| DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf |
| tmeissner/libvhdl |
19 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
other |
VHDL |
| Library of reusable VHDL components |
| abs-tudelft/vhdeps |
8 |
|
0 |
0 |
about 6 years ago |
12 |
October 25, 2019 |
7 |
apache-2.0 |
VHDL |
| VHDL dependency analyzer |
| kwonalbert/oram_fpga |
8 |
|
0 |
0 |
over 10 years ago |
0 |
|
2 |
|
VHDL |
| FPGA related files for ORAM |
| somaproject/backplane |
6 |
|
0 |
0 |
over 16 years ago |
0 |
|
0 |
|
VHDL |
| Soma Backplane Hardware |
