| SpinalHDL/VexRiscv |
2,135 |
|
0 |
0 |
over 2 years ago |
0 |
|
100 |
mit |
Assembly |
| A FPGA friendly 32 bit RISC-V CPU implementation |
| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| SI-RISCV/e200_opensource |
1,688 |
|
0 |
0 |
about 5 years ago |
0 |
|
33 |
apache-2.0 |
Verilog |
| Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2 |
| stnolting/neorv32 |
1,337 |
|
0 |
0 |
about 2 years ago |
0 |
|
15 |
bsd-3-clause |
VHDL |
| 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. |
| ZipCPU/zipcpu |
1,139 |
|
0 |
0 |
about 2 years ago |
0 |
|
4 |
|
Verilog |
| A small, light weight, RISC CPU soft core |
| riscv-mcu/e203_hbirdv2 |
741 |
|
0 |
0 |
about 3 years ago |
0 |
|
10 |
apache-2.0 |
Verilog |
| The Ultra-Low Power RISC-V Core |
| sergeykhbr/riscv_vhdl |
552 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
apache-2.0 |
Verilog |
| Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
| splinedrive/kianRiscV |
396 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
isc |
AGS Script |
| KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, . |
| T-K-233/RISC-V-Single-Cycle-CPU |
380 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
mit |
Verilog |
| A RISC-V 32bit single-cycle CPU written in Logisim |
| ultraembedded/riscv |
364 |
|
0 |
0 |
over 4 years ago |
0 |
|
4 |
bsd-3-clause |
Verilog |
| RISC-V CPU Core (RV32IM) |
