| circuitvalley/USB_C_Industrial_Camera_FPGA_USB3 |
610 |
|
0 |
0 |
over 2 years ago |
0 |
|
1 |
|
Verilog |
| Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source. |
| thinkoco/c5soc_opencl |
65 |
|
0 |
0 |
over 5 years ago |
0 |
|
8 |
apache-2.0 |
Verilog |
| DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on. |
| Elphel/x393 |
26 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
gpl-3.0 |
Verilog |
| mirror of https://git.elphel.com/Elphel/x393 |
| stevenbell/csirx |
25 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
lgpl-3.0 |
Verilog |
| Open-source CSI-2 receiver for Xilinx UltraScale parts |
| westonb/OV7670-Verilog |
23 |
|
0 |
0 |
over 7 years ago |
0 |
|
0 |
|
Verilog |
| Verilog modules required to get the OV7670 camera working |
| Elphel/eddr3 |
23 |
|
0 |
0 |
over 8 years ago |
0 |
|
0 |
|
Verilog |
| mirror of https://git.elphel.com/Elphel/eddr3 |
| Archfx/FPGA-stereo-Camera-Basys3 |
22 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
|
Verilog |
| Integration of two camera modules to Basys 3 FPGA |
| lllbbbyyy/FPGA-OV2640 |
17 |
|
0 |
0 |
over 5 years ago |
0 |
|
2 |
mit |
VHDL |
| This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA. |
| gtjennings1/UPDuino-OV7670-Camera |
17 |
|
0 |
0 |
about 8 years ago |
0 |
|
1 |
|
Verilog |
| Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module |
| jamesrivas/FPGA_Stereo_Depth_Map |
14 |
|
0 |
0 |
about 12 years ago |
0 |
|
0 |
|
Verilog |
