| funningboy/uvm_axi |
83 |
|
0 |
0 |
almost 13 years ago |
0 |
|
4 |
|
Verilog |
| uvm AXI BFM(bus functional model) |
| xver/Shunt |
29 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
other |
C |
| SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library) |
| ljgibbslf/SM3_core |
21 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
|
Verilog |
| rdiez/ethernet_dpi |
9 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
|
Verilog |
| DPI module for Ethernet-based interaction with Verilator simulations |
| rdiez/jtag_dpi |
9 |
|
0 |
0 |
over 13 years ago |
0 |
|
0 |
|
C++ |
| JTAG DPI module for OpenRISC simulation with Verilator |
| funningboy/smtdv |
8 |
|
0 |
0 |
over 9 years ago |
0 |
|
1 |
|
C++ |
| make your verilog DUT test more smart |
| witchard/sock.sv |
8 |
|
0 |
0 |
almost 11 years ago |
0 |
|
0 |
mit |
C |
| A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection. |
| rdiez/uart_dpi |
6 |
|
0 |
0 |
over 13 years ago |
0 |
|
1 |
|
Verilog |
| DPI module for UART-based console interaction with Verilator simulations |
