| sylefeb/Silice |
1,199 |
|
0 |
0 |
about 2 years ago |
0 |
|
73 |
other |
C++ |
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. |
| SteffenReith/J1Sc |
72 |
|
0 |
0 |
over 3 years ago |
0 |
|
0 |
bsd-3-clause |
Scala |
| A reimplementation of a tiny stack CPU |
| RuSys/Verugent |
46 |
|
0 |
0 |
almost 3 years ago |
4 |
January 22, 2020 |
1 |
apache-2.0 |
Rust |
| Verilog generation tool written in Rust |
| kazunori279/CPU32 |
26 |
|
0 |
0 |
about 12 years ago |
0 |
|
0 |
|
Verilog |
| Tiny MIPS for Terasic DE0 |
| kbob/icebreaker-candy |
24 |
|
0 |
0 |
almost 7 years ago |
0 |
|
1 |
gpl-3.0 |
Verilog |
| Eye candy from an iCEBreaker FPGA and a 64×64 LED panel |
| PrimeMHD/FPGA_ThreeLevelStorage |
23 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
gpl-3.0 |
Coq |
| 【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。 |
| hydronics2/HDMI-to-FPGA-to-APA102-Pixels |
17 |
|
0 |
0 |
almost 6 years ago |
0 |
|
0 |
|
Verilog |
| Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI. |
| mattvenn/ws2812-core |
17 |
|
0 |
0 |
over 4 years ago |
0 |
|
0 |
|
Verilog |
| verilog core for ws2812 leds |
| peepo/verilog_tutorials_BB |
16 |
|
0 |
0 |
about 10 years ago |
0 |
|
0 |
|
Verilog |
| verilog tutorials for iCE40HX8K Breakout Board |
| tinyvision-ai-inc/UPduino-v2.1 |
15 |
|
0 |
0 |
about 6 years ago |
0 |
|
3 |
mit |
Verilog |
| UPduino |
