| MiSTer-devel/ao486_MiSTer |
223 |
|
0 |
0 |
over 2 years ago |
0 |
|
46 |
other |
Verilog |
| ao486 port for MiSTer |
| ejrh/cpu |
73 |
|
0 |
0 |
about 11 years ago |
0 |
|
0 |
|
Verilog |
| A very primitive but hopefully self-educational CPU in Verilog |
| osresearch/up5k |
53 |
|
0 |
0 |
almost 5 years ago |
0 |
|
1 |
|
Verilog |
| Upduino v2 with the ice40 up5k FPGA demos |
| ZipCPU/dbgbus |
31 |
|
0 |
0 |
about 2 years ago |
0 |
|
0 |
|
Verilog |
| A collection of debugging busses developed and presented at zipcpu.com |
| gyurco/MiSTery |
30 |
|
0 |
0 |
over 2 years ago |
0 |
|
2 |
|
Verilog |
| Atari ST/STe core for FPGAs |
| antoinemadec/vim-verilog-instance |
22 |
|
0 |
0 |
about 3 years ago |
0 |
|
2 |
mit |
Python |
| verilog_instance.vim: create instantiation of ports from port declaration |
| janestreet/hardcaml_of_verilog |
15 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
mit |
OCaml |
| Convert Verilog to a Hardcaml design |
| AleksandarKostovic/SystemC-tutorial |
11 |
|
0 |
0 |
almost 7 years ago |
0 |
|
0 |
mit |
C++ |
| Brief SystemC getting started tutorial |
| ujamjar/hardcaml-yosys |
8 |
|
0 |
0 |
over 6 years ago |
0 |
|
3 |
isc |
Shell |
| [DEPRECATED] Import verilog designs into hardcaml using yosys |
| skiphansen/panog2_nes |
8 |
|
0 |
0 |
almost 4 years ago |
0 |
|
0 |
|
Verilog |
| Port of Brian Bennet's NES Emulator for the second generation Panologic thin client |
