| open-sdr/openwifi |
3,363 |
|
0 |
0 |
over 2 years ago |
0 |
|
51 |
agpl-3.0 |
C |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software |
| pConst/basic_verilog |
1,333 |
|
0 |
0 |
over 2 years ago |
0 |
|
0 |
|
Verilog |
| Must-have verilog systemverilog modules |
| google/xls |
1,087 |
|
0 |
0 |
about 2 years ago |
0 |
|
607 |
apache-2.0 |
C++ |
| XLS: Accelerated HW Synthesis |
| drom/awesome-hdl |
830 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
|
|
| Hardware Description Languages |
| open-sdr/openwifi-hw |
560 |
|
0 |
0 |
over 2 years ago |
0 |
|
5 |
agpl-3.0 |
Verilog |
| open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware |
| lastweek/fpga_readings |
249 |
|
0 |
0 |
almost 5 years ago |
0 |
|
3 |
apache-2.0 |
Verilog |
| Recipe for FPGA cooking |
| Nic30/hwt |
220 |
|
2 |
3 |
4 months ago |
34 |
July 01, 2021 |
7 |
mit |
Python |
| VHDL/Verilog/SystemC code generator, simulator API written in python/c++ |
| nlsynth/karuta |
87 |
|
0 |
0 |
about 4 years ago |
0 |
|
6 |
gpl-3.0 |
C++ |
| Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development. |
| jiangwx/SkrSkr |
76 |
|
0 |
0 |
almost 4 years ago |
0 |
|
4 |
other |
Tcl |
| The second place winner for DAC-SDC 2020 |
| TomG008/SkyNet |
75 |
|
0 |
0 |
about 6 years ago |
0 |
|
9 |
other |
Python |
