| platformio/platformio-atom-ide |
474 |
|
0 |
0 |
over 5 years ago |
0 |
|
20 |
apache-2.0 |
JavaScript |
| PlatformIO IDE for Atom: The next generation integrated development environment for IoT |
| EttusResearch/fpga |
192 |
|
0 |
0 |
over 4 years ago |
0 |
|
0 |
|
Verilog |
| The USRP™ Hardware Driver FPGA Repository |
| secworks/trng |
26 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
bsd-2-clause |
Verilog |
| True Random Number Generator core implemented in Verilog. |
| hsluoyz/Atalanta |
22 |
|
0 |
0 |
almost 13 years ago |
0 |
|
1 |
|
Verilog |
| Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University. |
| leonardt/verilogAST-cpp |
20 |
|
0 |
0 |
almost 3 years ago |
0 |
|
3 |
|
C++ |
| C++17 implementation of an AST for Verilog code generation |
| RAPcores/rapcores |
13 |
|
0 |
0 |
over 4 years ago |
0 |
|
28 |
isc |
Verilog |
| Robotic Application Processor |
| upscale-project/cosa2 |
11 |
|
0 |
0 |
almost 6 years ago |
0 |
|
14 |
other |
C++ |
| Next generation cosa. |
| icglue/icglue |
9 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
gpl-3.0 |
Tcl |
| A Tcl-Library for scripted HDL generation |
