| drom/awesome-hdl |
830 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
|
|
| Hardware Description Languages |
| olofk/edalize |
573 |
|
2 |
3 |
about 2 years ago |
24 |
December 08, 2023 |
91 |
bsd-2-clause |
Python |
| An abstraction library for interfacing EDA tools |
| JulianKemmerer/PipelineC |
519 |
|
0 |
0 |
about 2 years ago |
0 |
|
82 |
gpl-3.0 |
Python |
| A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. |
| VLSI-EDA/PoC |
324 |
|
0 |
0 |
over 5 years ago |
0 |
|
31 |
other |
VHDL |
| IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany |
| ghdl/ghdl-yosys-plugin |
270 |
|
0 |
0 |
over 2 years ago |
0 |
|
28 |
gpl-3.0 |
VHDL |
| VHDL synthesis (based on ghdl) |
| forflo/yodl |
96 |
|
0 |
0 |
about 9 years ago |
0 |
|
2 |
gpl-3.0 |
C++ |
| A VHDL frontend for Yosys |
| inforichland/freezing-spice |
88 |
|
0 |
0 |
over 7 years ago |
0 |
|
2 |
bsd-3-clause |
VHDL |
| A pipelined RISCV implementation in VHDL |
| Paebbels/JSON-for-VHDL |
61 |
|
0 |
0 |
over 3 years ago |
0 |
|
7 |
other |
VHDL |
| A JSON library implemented in VHDL. |
| tmeissner/psl_with_ghdl |
54 |
|
0 |
0 |
about 3 years ago |
0 |
|
1 |
lgpl-3.0 |
VHDL |
| Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) |
| FelixWinterstein/Vivado-KMeans |
42 |
|
0 |
0 |
over 8 years ago |
0 |
|
2 |
other |
VHDL |
| Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs |
