| PyHDI/Pyverilog |
466 |
|
11 |
10 |
almost 3 years ago |
24 |
December 30, 2020 |
64 |
apache-2.0 |
Python |
| Python-based Hardware Design Processing Toolkit for Verilog HDL |
| Nic30/hdlConvertor |
258 |
|
0 |
1 |
about 2 years ago |
19 |
July 02, 2021 |
30 |
mit |
C++ |
| Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4 |
| RuSys/Verugent |
46 |
|
0 |
0 |
almost 3 years ago |
4 |
January 22, 2020 |
1 |
apache-2.0 |
Rust |
| Verilog generation tool written in Rust |
| Nic30/hdlConvertorAst |
25 |
|
0 |
2 |
over 2 years ago |
11 |
October 23, 2023 |
3 |
mit |
Python |
| Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator |
| leonardt/verilogAST-cpp |
20 |
|
0 |
0 |
almost 3 years ago |
0 |
|
3 |
|
C++ |
| C++17 implementation of an AST for Verilog code generation |
| pheaver/netlist-verilog |
16 |
|
0 |
0 |
over 15 years ago |
0 |
|
5 |
|
Haskell |
| Netlist and Verilog Haskell Package |
| vegaluisjose/vast |
15 |
|
0 |
1 |
over 3 years ago |
8 |
November 20, 2022 |
2 |
apache-2.0 |
Rust |
| Verilog AST |
| dramforever/finlog |
9 |
|
0 |
0 |
over 5 years ago |
0 |
|
0 |
bsd-3-clause |
Haskell |
| Compiling finite generators to digital logic. WIP |
| rsnikhil/goParseBSV |
6 |
|
0 |
0 |
over 9 years ago |
0 |
|
0 |
mit |
Go |
| A standalone parser for BSV (Bluespec SystemVerilog) written in Go |
