| darklife/darkriscv |
1,795 |
|
0 |
0 |
over 2 years ago |
0 |
|
9 |
bsd-3-clause |
Verilog |
| opensouce RISC-V cpu core implemented in Verilog from scratch in one night! |
| sylefeb/Silice |
1,199 |
|
0 |
0 |
about 2 years ago |
0 |
|
73 |
other |
C++ |
| Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures. |
| T-K-233/RISC-V-Single-Cycle-CPU |
380 |
|
0 |
0 |
about 3 years ago |
0 |
|
0 |
mit |
Verilog |
| A RISC-V 32bit single-cycle CPU written in Logisim |
| jhshi/openofdm |
251 |
|
0 |
0 |
about 3 years ago |
0 |
|
8 |
apache-2.0 |
Verilog |
| Sythesizable, modular Verilog implementation of 802.11 OFDM decoder. |
| ZipCPU/dblclockfft |
195 |
|
0 |
0 |
about 2 years ago |
0 |
|
3 |
|
C++ |
| A configurable C++ generator of pipelined Verilog FFT cores |
| ZipCPU/autofpga |
153 |
|
0 |
0 |
about 2 years ago |
0 |
|
2 |
gpl-3.0 |
C++ |
| A utility for Composing FPGA designs from Peripherals |
| avakar/usbcorev |
146 |
|
0 |
0 |
over 3 years ago |
0 |
|
2 |
other |
Verilog |
| A full-speed device-side USB peripheral core written in Verilog. |
| ZipCPU/dspfilters |
119 |
|
0 |
0 |
about 2 years ago |
0 |
|
1 |
|
Verilog |
| A collection of demonstration digital filters |
| dan-rodrigues/icestation-32 |
107 |
|
0 |
0 |
over 4 years ago |
0 |
|
2 |
mit |
Verilog |
| Compact FPGA game console |
| hamsternz/DisplayPort_Verilog |
88 |
|
0 |
0 |
about 7 years ago |
0 |
|
1 |
mit |
Verilog |
| A Verilog implementation of DisplayPort protocol for FPGAs |
